Tribotechnical Diagnostics of Hydraulic Transfer Press

Import 02/11/2016Bakalářská práce se zabývá zjištěním stavu hydraulického postupového lisu pomocí tribotechnické diagnostiky. Práce je rozdělena do šesti kapitol. V první kapitole se nachází úvod do problematiky bakalářské práce. V druhé kapitole nalezneme informace o firmě, ve které se lis nachází, základní princip hydrauliky a obecné informace o postupových lisech. Ve třetí kapitole se nachází seznámení s konkrétním lisem, technickými údaji, mazacím systémem a provozu. Ve čtvrté kapitole nalezneme teoretickou problematiku tribodiagnostiky, metody měření použité v této práci a jejich princip. V páté kapitole nalezneme informace o odběru vzorků a hlavně výsledné hodnoty, naměřené v laboratoři. V poslední kapitole se nachází závěr práce.This bachelor thesis deals with finding out the condition of a hydraulic transfer press using tribotechnical diagnostic. It´s divided into six chapters. The first chapter includes the introduction of the topic of this thesis. The second chapter provides information about the company where the press is located, basic principle of hydraulics and general information about progressive presses. The third chapter will acquaint you with the specific press, technical specifications, lubrication systems and operation. In the fourth chapter we can find the theoretical problematic of the tribodiagnostic, measuring methods used in this thesis and their principles. The fifth chapter includes information about taking samples and mainly the results acquired in the laboratory. In the last chapter is the conclusion of the thesis.340 - Katedra výrobních strojů a konstruovánívýborn

Hardware Accelerator of Cartesian Genetic Programming with Multiple Fitness Units

A new accelerator of Cartesian genetic programming is presented in this paper. The accelerator is completely implemented in a single FPGA. The proposed architecture contains multiple instances of virtual reconfigurable circuit to evaluate several candidate solutions in parallel. An advanced memory organization was developed to achieve the maximum throughput of processing. The search algorithm is implemented using the on-chip PowerPC processor. In the benchmark problem (image filter evolution) the proposed platform provides a significant speedup (170) in comparison with a highly optimized software implementation. Moreover, the accelerator is 8 times faster than previous FPGA accelerators of image filter evolution

An Evolvable Combinational Unit for FPGAs

A complete hardware implementation of an evolvable combinational unit for FPGAs is presented. The proposed combinational unit consisting of a virtual reconfigurable circuit and evolutionary algorithm was described in VHDL independently of a target platform, i.e. as a soft IP core, and realized in the COMBO6 card. In many cases the unit is able to evolve (i.e. to design) the required function automatically and autonomously, in a few seconds, only on the basis of interactions with an environment. A number of circuits were successfully evolved directly in the FPGA, in particular, 3-bit multipliers, adders, multiplexers and parity encoders. The evolvable unit was also tested in a simulated dynamic environment and used to design various circuits specified by randomly generated truth tables

TPM Deployment Methodology

Diplomová práce se zabývá metodikou nasazení TPM. Úvod diplomové práce pojednává o teorii TPM,´5S, nasazení a využití technické diagnostika a systému online sledování. V další části je práce soustředěná na stěžejní stroj ve firmě. Následující kapitola se zabývá představením firmy, jejich výrobků a popsáním výrobního procesu. Poté už je práce orientovaná na shrnutí současného stavu ve firmě, jeho vyhodnocení a doporučení z pohledu údržby a TPM. Poté následuje kapitola, ve které je stěžejním tématem nalezení kritických bodů, jejich vyhodnocení a vyhledání nejvhodnějších metod pro efektivní údržbu. Poslední kapitolou je popis implementace do konkrétního výrobního závodu.The Master thesis deals with the methodology of TPM Deployment. The introduction of the Master thesis deals with the theory of TPM, 5S, deployment and use of Technical diagnostics and online monitoring system. In the next part is the work concentrated on the core machine in the company. The following chapter deals with introducing the company, its products and describing the production process. Then, the work is focused on summarizing the current state of the company, its evaluation and recommendations from the point of view of maintenance and TPM. Then, there is a chapter that focuses on finding critical points, evaluating them, and finding the most appropriate methods for effective maintenance. The last chapter is describing the implementation to a particular production plant.340 - Katedra výrobních strojů a konstruovánívýborn

Evaluating the Economic Performance of a Company Using Modern Methods of Financial Analysis

Tato diplomová práce se zabývá hodnocením výkonnosti společnosti LUHA zemědělská, a.s. pomocí moderních metod finanční analýzy. V této práci se analyzuje společnost pomocí tradičních a moderní metody ekonomické přidané hodnoty. Analýza je provedena za roky 2014 až 2018. Analýza pomocí tradičních metod zahrnuje absolutní ukazatele a poměrové ukazatele. Moderní metody použité v této diplomové práci jsou EVA Entity a EVA dle Ministerstva průmyslu a obchodu.This diploma thesis deals with the evaluation of the company LUHA zemědělská, a.s. using modern methods of financial analysis. In this work, the company analyzes traditional and modern methods of economic value added. The analysis is carried out for the years 2014 to 2018. Analysis using traditional methods involves absolute indicators and ratios. Modern methods used in this thesis are EVA Entity and EVA according to Ministry of Industry and Trade.152 - Katedra podnikohospodářskávelmi dobř

Evolvable Hardware as Non-Linear Predictor for Image Compression

Abstract. Evolvable hardware (EHW) is a new technology, which was discovered at intersection of artificial intelligence and the circuit design. Unique hardware architecture is searched for each task. The circuit connection is subject of evolution and the function of such circuit can adapt to dynamic changing environment. Genetic algorithm is used to simulate evolution – its chromosomes encode potential solutions (configuration bits of used reconfigurable chip). Simply, we can speak about hardware evolution. A concept for modelling of EHW and EHW-based applications is explained. Models of reconfigurable circuit and evolution are used in the application – lossy image compression – where EHW works as non-linear predictor for block of data. The new approach to compression quality control is described too. The results are compared with JPEG algorithm. Key words: genetic algorithm, evolvable hardware, image compression, modelling, prediction, reconfigurable circuit. Introduction: Evolvable hardware Engineers have been inspired by certain natural processes, which opened new domains as artificial neural networks and evolutionary algorithms. We need in our applications such qualifications as evolution, adaptation and fault tolerance that have difficult implementation using traditional methodologies, but the

R.: Design of the Special Fast Reconfigurable Chip Using Common FPGA

Abstract. Some applications require chips with fast partial reconfiguration. These requirements are traditionally satisfied by a special chip design, but it is usually a very expensive solution. This paper describes a new approach. Special fast partially reconfigurable chip is implemented with a common FPGA. The format of the configuration bit stream is suggested and optimized according to the given task. Result chip offers many good properties, but some problems with scalability can appear.

On Logic Synthesis of Conventionally Hard to Synthesize Circuits Using Genetic Programming

Abstract—Recently, it has been shown that synthesis of some circuits is quite difficult for conventional methods. In this paper we present a method of minimization of multi-level logic networks which can solve these difficult circuit instances. The synthesis problem is transformed on the search problem. A search algorithm called Cartesian genetic programming (CGP) is applied to synthesize various difficult circuits. Conventional circuit synthesis usually fails for these difficult circuits; specific synthesis processes must be employed to obtain satisfactory results. We have found that CGP is able to implicitly discover new efficient circuit structures. Thus, it is able to optimize circuits universally, regardless their structure. The circuit optimization by CGP has been found especially efficient when applied to circuits already optimized by a conventional synthesis. The total runtime is reduced, while the result quality is improved further more. Keywords-logic synthesis, multi-level network, genetic programming I